3.1: HWE.1 Hardware Requirements Analysis

Process Definition

Purpose

HWE.1 Purpose: To establish a set of hardware requirements from system requirements that will guide hardware design.

Outcomes

Base Practices with AI Integration

Hardware Requirement Types

Functional Requirements

Non-Functional Requirements

HW Requirements Derivation

From System to Hardware

The diagram below traces how system-level requirements decompose into hardware requirements, showing the derivation path from functional needs to electrical and physical specifications.

Interface Requirements

HW/SW Interface Specification

Note: The example below shows rendered markdown content for an interface specification.

---
ID: HWE-IF-001
Title: GPIO Interface for Door Lock Control
Type: Interface Requirement
Priority: Critical
---

## Description

The hardware shall provide GPIO interface for controlling four door
lock actuators with the following characteristics.

## Electrical Specification

| Parameter | Min | Typ | Max | Unit |
|-----------|-----|-----|-----|------|
| Output voltage (high) | 2.4 | 3.3 | 3.6 | V |
| Output voltage (low) | 0 | 0 | 0.4 | V |
| Output current (source) | - | - | 20 | mA |
| Output current (sink) | - | - | 25 | mA |
| Rise time | - | 10 | 50 | ns |
| Fall time | - | 10 | 50 | ns |

## Pin Assignment

| Pin | Port | Function | Direction |
|-----|------|----------|-----------|
| PA0 | GPIOA | DOOR_LOCK_FL | Output |
| PA1 | GPIOA | DOOR_LOCK_FR | Output |
| PA2 | GPIOA | DOOR_LOCK_RL | Output |
| PA3 | GPIOA | DOOR_LOCK_RR | Output |

## Timing Requirements

| Parameter | Value | Derived From |
|-----------|-------|--------------|
| Output propagation delay | < 100ns | HWE-BCM-010 |
| Register write to output | < 500ns | HWE-BCM-010 |

## Software Interface

Software module GPIO_Driver shall access these pins via memory-mapped
I/O at base address 0x40020000. See SWE.3 for driver implementation details.

## Traceability

- System: SYS-BCM-010
- Hardware: HWE-BCM-010, HWE-BCM-013
- Software: SWE-BCM-120

Memory Map Requirements

Register Definition

The following diagram shows the memory map specification, defining register addresses, bit fields, and access permissions that software must use to interact with hardware peripherals.

AI-Assisted Requirements Analysis

L1: Quality Analysis

AI Analysis of Hardware Requirements:
─────────────────────────────────────

HWE-BCM-010: "GPIO response time < 100ns"
├── Clarity: GOOD - Specific timing value
├── Testability: GOOD - Measurable parameter
├── Completeness: WARNING - Does not specify load conditions
└── Suggestion: Add "under 20mA load"

HWE-BCM-011: "CAN message latency < 5ms"
├── Clarity: WARNING - "Latency" not defined
├── Testability: NEEDS WORK - Define measurement points
├── Completeness: WARNING - Does not specify bus load
└── Suggestion: Clarify as "time from TX request to ACK"

HWE-BCM-012: "MCU interrupt latency < 1μs"
├── Clarity: WARNING - Which interrupt source?
├── Testability: GOOD - Measurable
├── Completeness: WARNING - Priority not specified
└── Suggestion: Specify interrupt source and priority level

Human Action Required:
• Review suggestions and update requirements
• Verify timing budgets with system architect
• Confirm interface with software team

L2: Consistency Checking

Interface Consistency Analysis:
──────────────────────────────

HW Requirement HWE-IF-001 vs SW Requirement SWE-IF-001:

[OK] Pin assignment consistent
[OK] Direction consistent (output)
[OK] Voltage levels compatible

[WARN] Potential Issue Found:
  HW: "Rise time: 10-50ns"
  SW: Assumes immediate transition

  Impact: SW timing calculation may be optimistic
  Recommendation: Add 50ns margin to SW timing budget

[OK] Memory addresses consistent
[OK] Register definitions aligned
[OK] Bit positions match

Consistency Score: 95% (1 minor issue)

Human Action: Review timing margin recommendation

Verification Criteria

Testability Matrix

Work Products

Summary

HWE.1 Hardware Requirements Analysis:

• AI Level: L1 (AI assists, human decides)
• Primary AI Value: Consistency checking, quality analysis
• Human Essential: Technical decisions, interface agreements
• Key Focus: HW/SW interface specification
• Critical Output: Interface Control Document (ICD)